Lithography aware timing analysis

ABSTRACT

A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of and priority to U.S. ProvisionalApplication No. 60/820,064, filed Jul. 21, 2006 and entitled“Lithography Aware Leakage and Timing Analysis,” the entire disclosureof which is hereby incorporated by reference for all purposes.

This application is related to co-pending U.S. patent application Ser.No. ______ , filed concurrently and entitled “Lithography Aware LeakageAnalysis” (Attorney Docket No. 026661-004610US), the entire disclosureof which is hereby incorporated by reference for all purposes.

BACKGROUND OF THE INVENTION

The present invention relates to the field of electronic designautomation. More specifically, the present invention relates toelectronic design automation including lithography aware leakage andtiming analysis.

Leakage has become a primary concern in the consumption of power insemiconductor chips. Timing also is a concern because it drives thecapability of the circuitry to make the calculations rapidly enough tomeet customer's requirements.

Historically power and timing were deterministically calculated oftenconsidering worst case analysis. Over time it has become obvious thatdeterministic calculation results in insufficient yield, especially aseach individual circuit component is considered from a worst caseperspective. Instead, statistical analysis may be used, realizing that arange of operation distribution exists for which most of thedistribution well meets customer requirements. This statistical analysishas come to be used on both timing analysis and more recently on leakageanalysis.

Leakage is a function of the overall transistor gate width in a givencircuit. Low threshold voltage FETs have significantly higher leakageand correspondingly higher performance. For multi-threshold voltageprocesses there are typically two levels. A low threshold (VT) devicefor high performance and a normal threshold device for lower power andlower performance. By selectively utilizing low threshold devices onlywhere needed, the performance requirement is met while keeping the powerconsumption relatively low. One method to approximate leakage currentwhich will be utilized by the chip is by totaling the cumulative FETgate width for each threshold device.

There are systematic variations and random variations which affecttiming and power. An example of a systematic variation would belithography defocus since this is a controllable parameter that affectsthe entire chip. A random variation would be due to a change in thenumber of dopant molecules since these can vary on a transistor bytransistor basis. These variations impact the overall design and can beused statistically to tune the design to meet timing and leakagerequirements.

Accordingly, what is desired are improved methods and apparatus forsolving the problems discussed above. Additionally, what is desired areimproved methods and apparatus for reducing some of the drawbacksdiscussed above.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to providing electronic design automationwith lithographic aware leakage and timing analysis.

In various embodiments, a method for performing leakage calculationsincludes receiving information specifying an integrated circuit. Aneighborhood of shapes associated with the integrated circuit isdetermined. Leakage information associated with the integrated circuitis generated based on the neighborhood of shapes.

Determining the neighborhood of shapes may include determining a firstset of spacings to a boundary of a first cell from an internal shape. Asecond set of spacings may be determined from the boundary of the firstcell to a shape of a second cell. A lithography process may becharacterized using the first and second set of spacings. In someembodiments, characterizing the lithography process may includecharacterizing effective transistor channel lengths as a function of thefirst and second set of spacings.

A mapping may be generated from the first and second set of spacings tothe lithography process. A mapping may be generated from the first andsecond set of spacings to leakage. Leakage of the first cell may becalculated based on the first and second set of spacing. The internalshape may include a polysilicon transistor shape. The internal shape mayalso include a wiring shape.

In one embodiment, a computer program product is stored on a computerreadable medium for performing leakage calculations. The computerprogram product includes code for receiving information specifying anintegrated circuit, code for determining a neighborhood of shapesassociated with the integrated circuit, and code for generating leakageinformation associated with the integrated circuit based on theneighborhood of shapes.

In a further embodiment, a system for performing leakage calculationsincludes a processor and a memory. The memory is coupled to theprocessor and stores a set of instructions which when executed by theprocessor cause the processor to receive information specifying anintegrated circuit, determine a neighborhood of shapes associated withthe integrated circuit, and generate leakage information associated withthe integrated circuit based on the neighborhood of shapes.

In various embodiments, a method for performing delay calculationsincludes receiving information specifying an integrated circuit. Aneighborhood of shapes associated with the integrated circuit isdetermined. Delay information associated with the integrated circuit isgenerated based on the neighborhood of shapes.

Determining the neighborhood of shapes may include determining a firstset of spacings to a boundary of a first cell from an internal shape. Asecond set of spacings may be determined from the boundary of the firstcell to a shape of a second cell. A lithography process may becharacterized using the first and second set of spacings. In someembodiments, characterizing the lithography process may includecharacterizing effective transistor channel lengths as a function of thefirst and second set of spacings.

A mapping may be generated from the first and second set of spacings tothe lithography process. A mapping may be generated from the first andsecond set of spacings to delay. Delay of the first cell may becalculated based on the first and second set of spacing. The internalshape may include a polysilicon transistor shape. The internal shape mayalso include a wiring shape.

In one embodiment, a computer program product is stored on a computerreadable medium for performing delay calculations. The computer programproduct includes code for receiving information specifying an integratedcircuit, code for determining a neighborhood of shapes associated withthe integrated circuit, and code for generating delay informationassociated with the integrated circuit based on the neighborhood ofshapes.

In a further embodiment, a system for performing delay calculationsincludes a processor and a memory. The memory is coupled to theprocessor and stores a set of instructions which when executed by theprocessor cause the processor to receive information specifying anintegrated circuit, determine a neighborhood of shapes associated withthe integrated circuit, and generate delay information associated withthe integrated circuit based on the neighborhood of shapes.

In various embodiments, a method for calculating neighborhood spacingsincludes receiving information specifying a plurality of cells. A firstset of spacings from a first shape associated with a first cell to aboundary associated with the first cell is determined. A second set ofspacings from the boundary to a second shape associated with a secondcell is determined. A neighborhood of shapes is generated based on thefirst and second set of spacings.

In one embodiment, a computer program product is stored on a computerreadable medium for calculating neighborhood spacings. The computerprogram product includes code for receiving information specifying aplurality of cells, code for determining a first set of spacings from afirst shape associated with a first cell to a boundary associated withthe first cell, code for determining a second set of spacings from theboundary to a second shape associated with a second cell, and code forgenerating a neighborhood of shapes based on the first and second set ofspacings.

In various embodiments, a method for determining circuit performanceincludes receiving information specifying an integrated circuit. Aneighborhood of shapes of a plurality of cells associated with theintegrated circuit is determined. A first set of spacings to a boundaryof at least one of the cells from an internal shape is determined. Asecond set of spacings from the boundary the cell to a shape associatedwith at least one of the plurality of cells is determined. A lithographyprocess is characterized using the first and second set of spacings. Amapping is generated from the first and second set of spacings toleakage. Leakage of the cells is calculated based on the first andsecond set of spacings. A mapping is generated from the first and secondset of spacings to delay. Delay of the cells is calculated based on thefirst and second set of spacings. Performance information associatedwith the integrated circuit is generated based on electrical connectionsbetween the cells and the calculated delays and leakages of the cells.

In one embodiment, a computer program product is stored on a computerreadable medium for determining circuit performance. The computerprogram product includes code for receiving information specifying anintegrated circuit, code for determining a neighborhood of shapes of aplurality of cells associated with the integrated circuit, code fordetermining a first set of spacings to a boundary of at least one of thecells from an internal shape, code for determining a second set ofspacings from the boundary the cell to a shape of at least one of theplurality of cells, code for characterizing a lithography process usingthe first and second set of spacings, code for generating a mapping fromthe first and second set of spacings to leakage, code for calculatingleakage of the cells based on the first and second set of spacings, codefor generatings a mapping from the first and second set of spacings todelay, code for calculating delay of the cells based on the first andsecond set of spacings, and code for generating performance informationassociated with the integrated circuit based on electrical connectionsbetween the cells and the calculated delays and leakages of the cells.

The features and advantages described in the specification are not allinclusive and, in particular, many additional features and advantageswill be apparent to one of ordinary skill in the art in view of thedrawings, specification, and claims. Moreover, it should be noted thatthe language used in the specification has been principally selected forreadability and instructional purposes, and may not have been selectedto delineate or circumscribe the inventive subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more fully understand the present invention, reference ismade to the accompanying drawings. Understanding that these drawings arenot to be considered limitations in the scope of the invention, thepresently described embodiments and the presently understood best modeof the invention are described with additional detail through use of theaccompanying drawings.

FIG. 1 illustrates a view of an original desired shape of an exemplaryportion of a circuit under design;

FIG. 2 illustrates a view of a desired shape with optical proximitycorrection (OPC) of the exemplary portion of the circuit under design ofFIG. 1;

FIG. 3 illustrates a view of the desired shape of FIG. 2 including afinal fabricated semiconductor shape;

FIG. 4 illustrates a view of a circuit under design with lithographycharacterization and spacing definition in one embodiment according tothe present invention;

FIG. 5 illustrates a view of a circuit under design showing boundarydistances in one embodiment according to the present invention;

FIG. 6 illustrates a flow chart of a methodology of simulating a circuitunder test using neighboring cells in one embodiment according to thepresent invention;

FIG. 7 illustrates a flow chart of a layout versus schematic methodologyin the methodology of FIG. 6 in one embodiment according to the presentinvention;

FIG. 8 illustrates a flow chart of a lithography characterizationmethodology of the methodology of FIG. 6 in one embodiment according tothe present invention;

FIG. 9 illustrates a flow chart of a boundary distance characterizationmethodology of the methodology of FIG. 6 in one embodiment according tothe present invention;

FIG. 10 illustrates a flow chart of a standard cell characterizationmethodology of the methodology of FIG. 6 in one embodiment according tothe present invention; and

FIG. 11 is a block diagram of typical computer system according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The figures and the following description relate to preferredembodiments of the present invention by way of illustration only. Itshould be noted that from the following discussion, alternativeembodiments of the structures and methods disclosed herein will bereadily recognized as viable alternatives that may be employed withoutdeparting from the principles of the claimed invention.

Reference will now be made in detail to several embodiments, examples ofwhich are illustrated in the accompanying figures. It is noted thatwherever practicable similar or like reference numbers may be used inthe figures and may indicate similar or like functionality. The figuresdepict embodiments of the present invention for purposes of illustrationonly. One skilled in the art will readily recognize from the followingdescription that alternative embodiments of the structures and methodsillustrated herein may be employed without departing from the principlesdescribed herein.

In general, Optical Proximity Correction (OPC) is a step in themanufacturing process that semiconductor manufactures employ to improvethe quality of high-performance integrated circuit designs such asmicroprocessors. The overall lithography process involves projecting acircuit design from a mask, through a complex lens system that reducesthe image onto a wafer that will later be divided into individual chips.These circuits contain tiny metal and polysilicon lines on the order of100 nm in width, in some cases smaller than the wavelength of the lightused to print them.

Several problems arise from the small size of these features and thefinite size and inherent limitations of the imaging system. First, thehigh frequency components required to reproduce the sharp edges inpolygon features may fall outside the lens. Secondly, stray lightentering the opening from one shape may find its way into another shapein close proximity, leading to a complex interaction of the electricfields of adjacent polygons. Thus, the final shapes will have roundedcorners and may bulge towards adjacent shapes, possibly shortingtogether and rendering the chip defective if the situation is badenough.

Optical Proximity Correction (OPC) is the process of modifying thepolygons that are drawn by the designers to compensate for the non-idealproperties of the lithography process. Given the shapes desired on thewafer, the mask is modified to improve the reproduction of the criticalgeometry. This is done by dividing polygon edges into small segments,moving the segments around, and by adding additional small polygons tostrategic locations in the layout. The addition of OPC features to themask layout allows for tighter design rules and significantly improvesprocess reliability and yield. The following figures demonstrate the useof and results of OPC.

FIG. 1 illustrates a view of an original desired shape of an exemplaryportion of a circuit under design. This shape normally has significantshortening on its ends and rounding of its corners during fabrication.OPC adds dumbbell shapes to prevent foreshortening and narrows or widenspieces to result in the proper final shapes.

FIG. 2 illustrates a view of a desired shape (dotted line) with opticalproximity correction of the exemplary portion of the circuit underdesign of FIG. 1. The solid line formed by the outline of the shapesindicates the OPC shape to accomplish the desired final shape.

FIG. 3 illustrates a view of the desired shape of FIG. 2 including afinal fabricated semiconductor shape. A line 301 indicates the finalfabricated shape. Without using OPC, the final shape would have lookedmuch worse and would not have approximated the original desired shape.

In various embodiments, systems and methods provide electronic designsimulation using the neighborhood environment of cells of the design todetermine the impact on both leakage and timing. The disclosed conceptutilizes knowledge both about the individual cells and about theneighborhood around the cells and the resulting impact on the fabricatedsemiconductors.

As discussed above, Optical proximity correction (OPC) considers the onchip shapes and the immediately adjacent shapes and corrects them tohave the final fabricated shape more closely reflect the original designintent. OPC, however, is insufficient to account for defocus associatedwith having multiple shapes adjacent to one another. As an example,wires with different spacings have different defocus sensitivities.Likewise, effective channel lengths (Leff) depend on the number andcloseness of other nearby channels.

In various embodiments, an electronic design automation (EDA) systemidentifies distances within individual cells. The distance between aspecific cell and its neighbor, along with information on that neighbor,is then factored into the leakage and timing analysis.

FIG. 4 illustrates a view of a circuit under design with lithographycharacterization and spacing definition. A cell outline is used for aplace and route (P&R) boundary 402. As illustrative examples, shapes404-1 and 404-2 of corresponding transistors are near the boundary 402of the cell. Because cells are typically assembled in a horizontallyadjacent fashion, only this direction is described. However, the presentinvention is not limited to one dimension, and may include, for example,two dimensional adjacency calculations. Spacings {s} are determined. Asan example of the spacing, a spacing s_ur denotes the upper-right spacebetween polysilicon shape 406-1 defining transistor channels in theboundary 402 and adjacent polysilicon shape 408-1. Similarly, spacingss_lr, s_ul, and s_ll denote lower-right, upper-left, and lower-leftspacings respectively. For clarity only two transistors 404 are shown,but the spacings s_ul and s_ll are spacings between two transistors andtwo polysilicon shapes that are not shown. In a two dimensionalanalysis, spacings for the right and left top and right and left bottommay be determined. Although the description is directed to transistorsand polysilicon transistor channel shapes, the analysis may be appliedto other elements, such as wiring shape.

To determine the information described in FIG. 4, the distances {b}within a cell, to nearby cell boundaries 402 are also determined. FIG. 5illustrates a view of a circuit under design showing boundary distancesto the boundary 402 from within a cell. For instance, the distance b_urdenotes the distance from within the cell to the upper-right boundary,again for polysilicon shapes. Similarly distances b_lr, b_ul, and b_lldenote lower-right, upper-left, and lower-left distances respectively.This information is collected for all cells in the library.

FIG. 6 illustrates a flow chart of a methodology of simulating a circuitunder test using neighboring cells. The processing depicted in FIG. 6may be performed by software modules (e.g., instructions or code)executed by a processor of a computer system, by hardware modules of thecomputer system, or combinations thereof.

Once the internal spacings {b} and the spacings {s} to neighboringcells, for a specific design, are considered, the appropriate delay andleakage may be calculated, based on a given defocus. The methodology ofthis calculation is now described.

Steps 602, 604, 606 and 608 are pre-characterization steps. The EDAsystem derives correspondence between transistor locations andtransistor names in a golden netlist (step 602) as described below inconjunction with FIG. 7. This is a layout versus schematic (LVS)process. The EDA system performs a lithography simulation process usinga boundary distance spacing (step 604) as described below in conjunctionwith FIG. 8. One example would be the characterization of effectivechannel lengths as a function of spacings. The EDA system characterizesboundary distances (step 606) as described below in conjunction withFIG. 9. In one embodiment delay or leakage is characterized as afunction of the effective channel lengths. The EDA system then mapsspacing to effective channel length and finally to delay and leakage(step 608) as described below in conjunction with FIG. 10.

Step 610 is a timing and leakage analysis step. The EDA system computestiming and leakage given the channel lengths determined based on theplaced cells and spacings (step 610).

The steps 602, 604, 606 and 608 are now described in conjunction withFIGS. 7, 8, 9, and 10, respectively.

FIG. 7 illustrates a flow chart of the deriving step 602. The result ofthis process is a transistor look up table that identifies location on aper cell basis. The EDA system imports a graphic design system file,such as a GDSII file, of a standard library (step 702), and imports thegolden netlist for all cells as well (step 704). The EDA systemdetermines correspondence between a transistor by name and thetransistor's location in the cell (step 706). The EDA system forms alook up table (LUT) describing the locations of the transistors on a percell basis (step 708). This transistor location look up table is usedfor all cells for OPC (block 710).

FIG. 8 illustrates a flow chart of a lithography simulation methodologyof the step 604. The resulting output is a new look up table describingthe spacings based on the lithographic simulation for each cell. The EDAsystem runs a lithographic simulation for all transistors as a functionof the spacing {s} for each cell (block 802). One embodimentcharacterizes the effective channel lengths versus spacing for allcells. The EDA system forms a look up table from the spacings {s} run inthe lithographic simulation (block 804). The lithographic simulationlook up table is formed for all cells (block 806).

FIG. 9 illustrates a flow chart of the boundary distancecharacterization step 606 of FIG. 6. One embodiment determines thespacing from the transistor channels to the boundary of the cell. Theresulting output is an enhancement to the look up table where boundarydistances are included for each cell. Using the LUT from step 806, theEDA system performs a design rule check (DRC) to determine the distances{b} that represent the distances of the boundary transistors 406 to theP&R boundary 402 (step 902). The EDA system inserts the distances {b}into the lithographic simulation look up table generated in step 806(step 904) to form an enhanced lithographic simulation look up table forall cells (step 906).

FIG. 10 illustrates a flow chart of a standard cell characterizationstep 608 of FIG. 6. The resulting output is a library (lib) file withthe delay or leakage information incorporated. The EDA system determinesthe Leff (step 1005) based on the spacing {s} to the surroundingstructures. The change in delay or the change in leakage based on achange in Leff is determined (step 1010). The delay or leakage for eachcell based on each transistor in each cell is determined based on eachtransistors Leff (step 1002). These Leff values are those determinedbased on the spacing {s}. A library file with the delay and leakageinformation (step 1004) is generated.

The calculation of step 1002 may be accomplished by either directcalculation, where all of the combinations of four spacings aretraversed. Alternatively the calculation can be accomplished by relatingthe spacings to effective channel lengths and then in turn relating themto leakage or delay. By example the direct delay calculation can berepresented as follows:

D=f(s _(—) ul,s _(—) ll,s _(—) ur,s _(—) lr)

Another embodiment has the delay related to the effective channellengths as follows:

D=f(g(s))

The terms in this equation indicate that the delay “D” is a function ofthe effective channel length “g”, which is in turn a function of thespacing “s” between channels.

For two dimensional analyses, the spacing {s} and distances {b} includedistances from the top and bottom of the cell. The width of channels andinterconnections are also accounted for in the analysis because of theimpact of the side of a channel or interconnection to neighboringdevices.

FIG. 11 is a simplified block diagram of a computer system 1100 that mayincorporate embodiments of the present invention. FIG. 11 is merelyillustrative of an embodiment incorporating the present invention anddoes not limit the scope of the invention as recited in the claims. Oneof ordinary skill in the art would recognize other variations,modifications, and alternatives.

In one embodiment, computer system 1100 typically includes a monitor1110, a computer 1120, user output devices 1130, user input devices1140, communications interface 1150, and the like.

As shown in FIG. 11, computer 1120 may include a processor(s) 1160 thatcommunicates with a number of peripheral devices via a bus subsystem1190. These peripheral devices may include user output devices 1130,user input devices 1140, communications interface 1150, and a storagesubsystem, such as random access memory (RAM) 1170 and disk drive 1180.

User input devices 1130 include all possible types of devices andmechanisms for inputting information to computer system 1120. These mayinclude a keyboard, a keypad, a touch screen incorporated into thedisplay, audio input devices such as voice recognition systems,microphones, and other types of input devices. In various embodiments,user input devices 1130 are typically embodied as a computer mouse, atrackball, a track pad, a joystick, wireless remote, drawing tablet,voice command system, eye tracking system, and the like. User inputdevices 1130 typically allow a user to select objects, icons, text andthe like that appear on the monitor 1110 via a command such as a clickof a button or the like.

User output devices 1140 include all possible types of devices andmechanisms for outputting information from computer 1120. These mayinclude a display (e.g., monitor 1110), non-visual displays such asaudio output devices, etc.

Communications interface 1150 provides an interface to othercommunication networks and devices. Communications interface 1150 mayserve as an interface for receiving data from and transmitting data toother systems. Embodiments of communications interface 1150 typicallyinclude an Ethernet card, a modem (telephone, satellite, cable, ISDN),(asynchronous) digital subscriber line (DSL) unit, FireWire interface,USB interface, and the like. For example, communications interface 1150may be coupled to a computer network, to a FireWire bus, or the like. Inother embodiments, communications interfaces 1150 may be physicallyintegrated on the motherboard of computer 1120, and may be a softwareprogram, such as soft DSL, or the like.

In various embodiments, computer system 1100 may also include softwarethat enables communications over a network such as the HTTP, TCP/IP,RTP/RTSP protocols, and the like. In alternative embodiments of thepresent invention, other communications software and transfer protocolsmay also be used, for example IPX, UDP or the like.

In some embodiment, computer 1120 includes one or more Xeonmicroprocessors from Intel as processor(s) 1160. Further, oneembodiment, computer 1120 includes a UNIX-based operating system.

RAM 1170 and disk drive 1180 are examples of tangible media configuredto store data such as embodiments of the present invention, includingexecutable computer code, human readable code, or the like. Other typesof tangible media include floppy disks, removable hard disks, opticalstorage media such as CD-ROMS, DVDs and bar codes, semiconductormemories such as flash memories, read-only-memories (ROMS),battery-backed volatile memories, networked storage devices, and thelike. RAM 1170 and disk drive 1180 may be configured to store the basicprogramming and data constructs that provide the functionality of thepresent invention.

Software code modules and instructions that provide the functionality ofthe present invention may be stored in RAM 1170 and disk drive 1180.These software modules may be executed by processor(s) 1160. RAM 1170and disk drive 1180 may also provide a repository for storing data usedin accordance with the present invention.

RAM 1170 and disk drive 1180 may include a number of memories includinga main random access memory (RAM) for storage of instructions and dataduring program execution and a read only memory (ROM) in which fixedinstructions are stored. RAM 1170 and disk drive 1180 may include a filestorage subsystem providing persistent (non-volatile) storage forprogram and data files. RAM 1170 and disk drive 1180 may also includeremovable storage systems, such as removable flash memory.

Bus subsystem 1190 provides a mechanism for letting the variouscomponents and subsystems of computer 1120 communicate with each otheras intended. Although bus subsystem 1190 is shown schematically as asingle bus, alternative embodiments of the bus subsystem may utilizemultiple busses.

FIG. 11 is representative of a computer system capable of embodying thepresent invention. It will be readily apparent to one of ordinary skillin the art that many other hardware and software configurations aresuitable for use with the present invention. For example, the computermay be a desktop, portable, rack-mounted or tablet configuration.Additionally, the computer may be a series of networked computers.Further, the use of other micro processors are contemplated, such asPentium™ or Itanium™ microprocessors; Opteron™ or AthlonXP™microprocessors from Advanced Micro Devices, Inc; and the like. Further,other types of operating systems are contemplated, such as Windows®,WindowsXP®, WindowsNT®, or the like from Microsoft Corporation, Solarisfrom Sun Microsystems, LINUX, UNIX, and the like. In still otherembodiments, the techniques described above may be implemented upon achip or an auxiliary processing board.

The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense. It will, however, beevident that various modifications and changes may be made thereuntowithout departing from the broader spirit and scope of the invention asset forth in the claims. In addition, the technique and system of thepresent invention is suitable for use with a wide variety of EDA toolsand methodologies for programming a device. The scope of the inventionshould, therefore, be determined not with reference to the abovedescription, but instead should be determined with reference to thepending claims along with their full scope or equivalents.

The present invention can be implemented in the form of control logic insoftware or hardware or a combination of both. The control logic may bestored in an information storage medium as a plurality of instructionsadapted to direct an information-processing device to perform a set ofsteps disclosed in embodiments of the present invention. Based on thedisclosure and teachings provided herein, a person of ordinary skill inthe art will appreciate other ways and/or methods to implement thepresent invention.

The embodiments discussed herein are illustrative of one or moreexamples of the present invention. As these embodiments of the presentinvention are described with reference to illustrations, variousmodifications or adaptations of the methods and/or specific structuresdescribed may become apparent to those skilled in the art. All suchmodifications, adaptations, or variations that rely upon the teachingsof the present invention, and through which these teachings haveadvanced the art, are considered to be within the scope of the presentinvention. Hence, the present descriptions and drawings should not beconsidered in a limiting sense, as it is understood that the presentinvention is in no way limited to only the embodiments illustrated.

The above description is illustrative but not restrictive. Manyvariations of the invention will become apparent to those skilled in theart upon review of the disclosure. The scope of the invention should,therefore, be determined not with reference to the above description,but instead should be determined with reference to the pending claimsalong with their full scope or equivalents.

1. A method for performing delay calculations, the method comprising:receiving information specifying an integrated circuit; determining aneighborhood of shapes associated with the integrated circuit; andgenerating delay information associated with the integrated circuitbased on the neighborhood of shapes.
 2. The method of claim 1 whereindetermining the neighborhood of shapes comprises: determining a firstset of spacings to a boundary of a first cell from an internal shape;determining a second set of spacings from the boundary of the first cellto a shape of a second cell; and characterizing a lithography processusing the first and second set of spacings.
 3. The method of claim 2wherein characterizing the lithography process comprises characterizingeffective transistor channel lengths as a function of the first andsecond set of spacings.
 4. The method of claim 2 further comprisinggenerating a mapping from the first and second set of spacings to thelithography process.
 5. The method of claim 2 further comprisinggenerating a mapping from the first and second set of spacings to delay.6. The method of claim 5 further comprising calculating delay of thefirst cell based on the first and second set of spacing.
 7. The methodof claim 2 wherein the internal shape comprises a polysilicon transistorshape.
 8. The method of claim 2 wherein the internal shape comprises awiring shape.
 9. A computer program product stored on a computerreadable medium for performing delay calculations, the computer programproduct comprising: code for receiving information specifying anintegrated circuit; code for determining a neighborhood of shapesassociated with the integrated circuit; and code for generating delayinformation associated with the integrated circuit based on theneighborhood of shapes.
 10. The computer program product of claim 9wherein the code for determining the neighborhood of shapes comprises:code for determining a first set of spacings to a boundary of a firstcell from an internal shape; code for determining a second set ofspacings from the boundary of the first cell to a shape of a secondcell; and code for characterizing a lithography process using the firstand second set of spacings.
 11. The computer program product of claim 10wherein the code for characterizing the lithography process comprisescode for characterizing effective transistor channel lengths as afunction of the first and second set of spacings.
 12. The computerprogram product of claim 10 further comprising code for generating amapping from the first and second set of spacings to the lithographyprocess.
 13. The computer program product of claim 10 further comprisingcode for generating a mapping from the first and second set of spacingsto delay and calculating delay of the first cell based on the first andsecond set of spacings.
 14. The computer program product of claim 10wherein the internal shape comprises a polysilicon transistor shape. 15.A system for performing delay calculations, the system comprising: aprocessor; and a memory coupled to the processor, the memory configuredto store a set of instructions which when executed by the processorcause the processor to: receive information specifying an integratedcircuit; determine a neighborhood of shapes associated with theintegrated circuit; and generate delay information associated with theintegrated circuit based on the neighborhood of shapes.
 16. The systemof claim 15 wherein the processor is further caused to: determine afirst set of spacings to a boundary of a first cell from an internalshape; determine a second set of spacings from the boundary of the firstcell to a shape of a second cell; and characterize a lithography processusing the first and second set of spacings to determine the neighborhoodof shapes.
 17. The system of claim 16 wherein the processor is caused tocharacterize effective transistor channel lengths as a function of thefirst and second set of spacings to characterize the lithographyprocess.
 18. The system of claim 16 wherein the processor is furthercaused to generate a mapping from the first and second set of spacingsto the lithography process.
 19. The system of claim 16 wherein theprocessor is further caused to generate a mapping from the first andsecond set of spacings to delay and calculate delay of the first cellbased on the first and second set of spacings.
 20. The system of claim16 wherein the internal shape comprises a polysilicon transistor shape.